1. Field of the Invention
This invention relates to FIFO circuits, and more particularly to low latency FIFO designs that interface subsystems working at different speeds or between subsystems with very long interconnection delays.
2. Background of Related Art
A trend in VLSI is increasingly towards a “system-on-a-chip” involving many clock domains. A challenging problem is to robustly interface these domains. There have been few adequate solutions, especially ones providing reliable low-latency communication.
A number of FIFO designs and components have been developed to handle timing discrepancies between subsystems. Some designs are limited to handling single-clock systems. These approaches have been proposed to handle clock skew, draft, and jitter, and very long interconnect penalties.
Several designs have also been proposed to handle mixed-timing domains. One category of design approaches attempts to synchronize data items and/or control signals with the receiver, without interfering with its clock. In particular, Seizovic robustly interfaces asynchronous with synchronous environments through a “synchronization FIFO”. (J. Seizovic, “Pipeline Synchronization,” Proceedings Internat'l Synposium on Advanced Research in Asynchronous Circuits and Systems, pp. 87–96, November 1994.) However, the latency of his design is proportional with the number of FIFO stages, whose implementation includes expensive synchronizers. Furthermore, his design requires the sender to produce data items at a constant rate.
Other designs achieve robust interfacing of mixed-clock systems. However, these designs temporarily modify the receiver's clock. Synchronization failures are avoided by pausing or stretching the receiver's local clock. Each communicating synchronous system is wrapped with asynchronous logic, which is responsible for communicating with the other systems and for adjusting the clocks. This approach changes the local systems' clocks, and may introduce latency penalties in restarting them.
It is therefore an object of the invention to produce a low-latency, high-throughput FIFO design which robustly accommodate mixed-clock systems.
It is also an object of the invention to provide a mixed-clock systems in which only control signals are synchronized to avoid expensive synchronization.